In SOI technology a thin silicon layer is formed over an insulating layer, such as silicon oxide, which in turn is formed over a bulk substrate. This insulating layer is often referred to as a buried oxide (BOX) layer or simply as a BOX. For a single BOX SOI wafer the silicon layer can be divided into active regions by shallow trench isolation (STI) which intersects the BOX and provides total isolation for active device regions formed in the silicon layer. Sources and drains of field effect transistors (FETs) can be formed, for example, by the growth of in-situ doped silicon or by ion implantation of N-type and P-type dopant material into the silicon layer. A field effect transistor channel region between a source/drain pair can be created so as to underlie a gate structure using, for example, an elongated ‘fin’ structure that is defined in the silicon layer when a FinFET device is being fabricated.
One problem that can be present in a conventional FinFET device is the presence of a substantial amount of parasitic resistance and capacitance, both of which can detrimentally affect the device performance.